# Project-Wide Assignments
# ========================
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_C10 -to S1
set_location_assignment PIN_B8 -to D0
set_location_assignment PIN_A7 -to D1
set_location_assignment PIN_B11 -to Y

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name TOP_LEVEL_ENTITY adder16s

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE 10M50DAF484C6GES
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"

# =====================
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"

set_global_assignment -name SEED 1
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF

set_global_assignment -name VERILOG_FILE adder16s.v

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top


set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name BOARD "MAX 10 DE10 - Lite"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top